The present invention relates generally to integrated circuits, and more particularly to metal patterning processes for use in manufacturing integrated circuits based on subtractive etching of silver.
Integrated circuits (ICs) commonly use copper interconnects (or “lines”) to connect semiconductor devices such as, for example, transistors, on the ICs. These interconnects are typically formed using an additive damascene process in which an interconnect dielectric material is patterned to include at least one opening therein. Copper is subsequently deposited within the opening and thereafter any copper that is located outside the at least one opening can be removed via a planarization process. Successive layers of interconnect dielectric and copper can be formed using such an additive damascene process resulting in a multilayered copper interconnect structure.
Conventional damascene processing such as that described above is not always compatible with the trend toward smaller feature sizes in modern complementary metal oxide semiconductor (CMOS) technology. For instance, modern CMOS technology may require line widths of less than forty nanometers and aspect ratios (i.e., line height to line width) of approximately 2 to 1. Attempting conventional damascene processing within these parameters often results in poor liner/seed coverage on the walls of the openings formed into the interconnect dielectric material, and reentrant profiles. Consequently, the copper filling the at least one opening is subject to voids, defects, and poor adhesion to the liner material. Moreover, as the lines narrow in size, the resistivity of the copper is increased (due to, for example, the thickness of the liner relative to the copper, the small copper grain size, and copper grain boundary and surface scattering phenomena), resulting in decreased IC performance.